Microcontrollers are systems on a chip that comprise a microprocessor, memory, and a plurality of integrated peripheral devices. A wide variety of microcontrollers such as 8-bit, 16-bit, and 32-bit microcontrollers are available. While the 16-bit and 32-bit microcontrollers provide for large data memory, memories in the 8-bit microcontrollers are generally limited due to the architecture of the device. 8-bit microcontrollers are still very popular and used in many applications. To keep the cost low, certain 8-bit microcontrollers are designed with a very limited amount of data memory, for example not more than 4096 bits. The reason for such limitations lie in the instructions size and the limited addressing logic.
FIG. 1 shows a typical architecture of such a low cost 8-Bit microcontroller manufactured by the Assignee of the present application using a memory banking technology to reduce the complexity of the processor. As can be seen such a microcontroller is designed according to the Harvard architecture and allows for various addressing modes of the data memory. For example, the 16-bit instruction word is designed to carry up to 12 address bits that can address up to 4096 memory locations. If less than 12 bits are provided by an instruction due to a larger op-code, a memory banking mechanism is used. Then the respective bits of an instruction can be combined with 4 bits provided by a bank select register BSR. A plurality of indirect address register FSR can be provided which may each address the full memory space of the data memory and therefore these registers use 12 bits. An access bank can be used to temporarily switch to a predefined bank based on a specific bit setting in the instruction. The predefined memory bank can be, e.g., memory-mapped to the most important special function registers. Thus changes in these registers can be performed independent of which memory bank is currently selected with a minimum of delay. Thus, even with a 16-bit instruction word length, an 8-bit microcontroller is limited in the amount of data memory that can be reasonably supported by the architecture.